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[/] [mlite/] [trunk/] [vhdl/] - Rev 120

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Rev Log message Author Age Path
120 Make generics "GENERIC" rhoads 7468d 23h /mlite/trunk/vhdl/
119 Opcodes from count.c rhoads 7507d 10h /mlite/trunk/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7507d 10h /mlite/trunk/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7507d 10h /mlite/trunk/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7507d 10h /mlite/trunk/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7507d 10h /mlite/trunk/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7507d 10h /mlite/trunk/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7507d 10h /mlite/trunk/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7507d 11h /mlite/trunk/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7781d 07h /mlite/trunk/vhdl/
107 merged rising_edge(clk) statements rhoads 7781d 07h /mlite/trunk/vhdl/
106 better test mem_pause rhoads 7784d 09h /mlite/trunk/vhdl/
105 better test mem_pause rhoads 7784d 09h /mlite/trunk/vhdl/
103 shorten similation times rhoads 7785d 08h /mlite/trunk/vhdl/
102 permit testing mem_pause rhoads 7785d 08h /mlite/trunk/vhdl/
101 Correctly freeze the pipeline when mem_pause = '1' rhoads 7785d 08h /mlite/trunk/vhdl/
99 correct upper 32-bits for mult(-1,-1) rhoads 7927d 08h /mlite/trunk/vhdl/
98 Fix size of GENERIC ram. rhoads 7932d 06h /mlite/trunk/vhdl/
97 added documentation rhoads 7996d 12h /mlite/trunk/vhdl/
96 Simplify take_branch rhoads 8030d 14h /mlite/trunk/vhdl/

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