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[/] [mlite/] [trunk/] [vhdl/] - Rev 123

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Rev	Log message	Author	Age	Path
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7405d 07h	/mlite/trunk/vhdl/
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7469d 07h	/mlite/trunk/vhdl/
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7480d 20h	/mlite/trunk/vhdl/
120	Make generics "GENERIC"	rhoads	7480d 20h	/mlite/trunk/vhdl/
119	Opcodes from count.c	rhoads	7519d 07h	/mlite/trunk/vhdl/
118	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7519d 07h	/mlite/trunk/vhdl/
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7519d 07h	/mlite/trunk/vhdl/
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7519d 07h	/mlite/trunk/vhdl/
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7519d 07h	/mlite/trunk/vhdl/
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7519d 07h	/mlite/trunk/vhdl/
113	Matthias Grunewald's bug fixes: Branch and compare instructions didn't interpret immediate as signed.	rhoads	7519d 07h	/mlite/trunk/vhdl/
112	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7519d 07h	/mlite/trunk/vhdl/
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7793d 03h	/mlite/trunk/vhdl/
107	merged rising_edge(clk) statements	rhoads	7793d 03h	/mlite/trunk/vhdl/
106	better test mem_pause	rhoads	7796d 06h	/mlite/trunk/vhdl/
105	better test mem_pause	rhoads	7796d 06h	/mlite/trunk/vhdl/
103	shorten similation times	rhoads	7797d 05h	/mlite/trunk/vhdl/
102	permit testing mem_pause	rhoads	7797d 05h	/mlite/trunk/vhdl/
101	Correctly freeze the pipeline when mem_pause = '1'	rhoads	7797d 05h	/mlite/trunk/vhdl/
99	correct upper 32-bits for mult(-1,-1)	rhoads	7939d 04h	/mlite/trunk/vhdl/

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[/] [mlite/] [trunk/] [vhdl/] - Rev 123

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