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Rev Log message Author Age Path
125 Fixed pc_source_type comment. rhoads 7343d 08h /mlite/trunk/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7343d 08h /mlite/trunk/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7410d 09h /mlite/trunk/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7474d 09h /mlite/trunk/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7485d 22h /mlite/trunk/vhdl/
120 Make generics "GENERIC" rhoads 7485d 22h /mlite/trunk/vhdl/
119 Opcodes from count.c rhoads 7524d 09h /mlite/trunk/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 09h /mlite/trunk/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 09h /mlite/trunk/vhdl/
116 Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 09h /mlite/trunk/vhdl/
115 Matthias Grunewald's changes for Xilinx FPGA dual-port RAM. rhoads 7524d 09h /mlite/trunk/vhdl/
114 Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II. rhoads 7524d 09h /mlite/trunk/vhdl/
113 Matthias Grunewald's bug fixes:
Branch and compare instructions didn't interpret immediate as signed.		 rhoads 7524d 09h /mlite/trunk/vhdl/
112 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7524d 09h /mlite/trunk/vhdl/
108 changed interrupt vector from 0x30 to 0x3c rhoads 7798d 05h /mlite/trunk/vhdl/
107 merged rising_edge(clk) statements rhoads 7798d 05h /mlite/trunk/vhdl/
106 better test mem_pause rhoads 7801d 08h /mlite/trunk/vhdl/
105 better test mem_pause rhoads 7801d 08h /mlite/trunk/vhdl/
103 shorten similation times rhoads 7802d 07h /mlite/trunk/vhdl/
102 permit testing mem_pause rhoads 7802d 07h /mlite/trunk/vhdl/

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