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[/] [mlite/] [trunk/] [vhdl/] - Rev 194

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Rev Log message Author Age Path
194 Implemented BREAK and SYSCALL opcodes rhoads 6344d 07h /mlite/trunk/vhdl/
186 Change memory_type to "XILINX_16X" rhoads 6361d 01h /mlite/trunk/vhdl/
185 Latest opcodes from count.c rhoads 6376d 03h /mlite/trunk/vhdl/
184 Fix comment rhoads 6376d 03h /mlite/trunk/vhdl/
181 Fix typo in comment rhoads 6376d 04h /mlite/trunk/vhdl/
180 Easily permit full UART simulation rhoads 6376d 04h /mlite/trunk/vhdl/
139 Major changes -- updated to Plasma Version 3 rhoads 6690d 00h /mlite/trunk/vhdl/
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7169d 23h /mlite/trunk/vhdl/
131 Changed "GENERIC" to "DEFAULT" to be Xilinx friendly. rhoads 7169d 23h /mlite/trunk/vhdl/
129 Added reset_in to sensitivity list rhoads 7188d 23h /mlite/trunk/vhdl/
128 Reset all registers, constants now upper case. rhoads 7307d 10h /mlite/trunk/vhdl/
125 Fixed pc_source_type comment. rhoads 7326d 00h /mlite/trunk/vhdl/
124 Holger Lohn's fix for interrupts when 3-state pipeline enabled. rhoads 7326d 00h /mlite/trunk/vhdl/
123 Uncomment out the Altera portion. Xilinx users may need to re-comment out this section. rhoads 7393d 00h /mlite/trunk/vhdl/
122 Added comment to explain why c_bus isn't delayed but reg_dest is delayed. rhoads 7457d 00h /mlite/trunk/vhdl/
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7468d 13h /mlite/trunk/vhdl/
120 Make generics "GENERIC" rhoads 7468d 13h /mlite/trunk/vhdl/
119 Opcodes from count.c rhoads 7507d 00h /mlite/trunk/vhdl/
118 Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7507d 00h /mlite/trunk/vhdl/
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7507d 00h /mlite/trunk/vhdl/

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