URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 25

Rev	Log message	Author	Age	Path
25	opcodes target	rhoads	8215d 04h	/mlite/trunk/vhdl/
24	Disable interrupts upon reset.	rhoads	8215d 04h	/mlite/trunk/vhdl/
23	Fixed div -x/y.	rhoads	8215d 04h	/mlite/trunk/vhdl/
19	Changed simili run to 40us.	rhoads	8217d 04h	/mlite/trunk/vhdl/
18	Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0.	rhoads	8217d 04h	/mlite/trunk/vhdl/
17	Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces.	rhoads	8217d 04h	/mlite/trunk/vhdl/
13	Removed reg_bank configuration control	rhoads	8221d 04h	/mlite/trunk/vhdl/
12	Better support for dual-port memories, removed old method	rhoads	8221d 04h	/mlite/trunk/vhdl/
11	Added comment for DEBUG mode	rhoads	8221d 04h	/mlite/trunk/vhdl/
10	Add pause_in to process dependency, fixes "lw $4,0($4)"	rhoads	8221d 04h	/mlite/trunk/vhdl/
9	Support for generic_tpram dual-port RAM	rhoads	8226d 07h	/mlite/trunk/vhdl/
8	Preparing to use dual-port memory for registers.	rhoads	8227d 05h	/mlite/trunk/vhdl/
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8232d 12h	/mlite/trunk/vhdl/
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8236d 10h	/mlite/trunk/vhdl/
2	MIPS-lite CPU core	rhoads	8455d 10h	/mlite/trunk/vhdl/