URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 261

Rev	Log message	Author	Age	Path
261	Removed commented out lines	rhoads	6052d 15h	/mlite/trunk/vhdl/
260	Removed Xilinx use statements	rhoads	6052d 15h	/mlite/trunk/vhdl/
259	Support for DDR	rhoads	6052d 15h	/mlite/trunk/vhdl/
238	Xilinx Spartan-3 board pinout file	rhoads	6239d 05h	/mlite/trunk/vhdl/
204	Added comment about delaying reg_dest	rhoads	6290d 12h	/mlite/trunk/vhdl/
203	Fixed stages comment	rhoads	6291d 16h	/mlite/trunk/vhdl/
202	Defined outputing PC as stage #0	rhoads	6291d 17h	/mlite/trunk/vhdl/
196	Explained how to remove mult.vhd and use SW multiplication and division.	rhoads	6339d 09h	/mlite/trunk/vhdl/
194	Implemented BREAK and SYSCALL opcodes	rhoads	6356d 12h	/mlite/trunk/vhdl/
186	Change memory_type to "XILINX_16X"	rhoads	6373d 06h	/mlite/trunk/vhdl/
185	Latest opcodes from count.c	rhoads	6388d 08h	/mlite/trunk/vhdl/
184	Fix comment	rhoads	6388d 08h	/mlite/trunk/vhdl/
181	Fix typo in comment	rhoads	6388d 09h	/mlite/trunk/vhdl/
180	Easily permit full UART simulation	rhoads	6388d 09h	/mlite/trunk/vhdl/
139	Major changes -- updated to Plasma Version 3	rhoads	6702d 05h	/mlite/trunk/vhdl/
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7182d 04h	/mlite/trunk/vhdl/
131	Changed "GENERIC" to "DEFAULT" to be Xilinx friendly.	rhoads	7182d 04h	/mlite/trunk/vhdl/
129	Added reset_in to sensitivity list	rhoads	7201d 04h	/mlite/trunk/vhdl/
128	Reset all registers, constants now upper case.	rhoads	7319d 15h	/mlite/trunk/vhdl/
125	Fixed pc_source_type comment.	rhoads	7338d 05h	/mlite/trunk/vhdl/