URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 265

Rev	Log message	Author	Age	Path
265	Changed write_byte_enable to byte_we	rhoads	6178d 16h	/mlite/trunk/vhdl/
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6178d 16h	/mlite/trunk/vhdl/
263	Changed write_byte_enable to byte_we	rhoads	6178d 16h	/mlite/trunk/vhdl/
262	Changed comment	rhoads	6178d 16h	/mlite/trunk/vhdl/
261	Removed commented out lines	rhoads	6178d 16h	/mlite/trunk/vhdl/
260	Removed Xilinx use statements	rhoads	6178d 16h	/mlite/trunk/vhdl/
259	Support for DDR	rhoads	6178d 16h	/mlite/trunk/vhdl/
238	Xilinx Spartan-3 board pinout file	rhoads	6365d 06h	/mlite/trunk/vhdl/
204	Added comment about delaying reg_dest	rhoads	6416d 13h	/mlite/trunk/vhdl/
203	Fixed stages comment	rhoads	6417d 17h	/mlite/trunk/vhdl/
202	Defined outputing PC as stage #0	rhoads	6417d 17h	/mlite/trunk/vhdl/
196	Explained how to remove mult.vhd and use SW multiplication and division.	rhoads	6465d 09h	/mlite/trunk/vhdl/
194	Implemented BREAK and SYSCALL opcodes	rhoads	6482d 13h	/mlite/trunk/vhdl/
186	Change memory_type to "XILINX_16X"	rhoads	6499d 06h	/mlite/trunk/vhdl/
185	Latest opcodes from count.c	rhoads	6514d 09h	/mlite/trunk/vhdl/
184	Fix comment	rhoads	6514d 09h	/mlite/trunk/vhdl/
181	Fix typo in comment	rhoads	6514d 10h	/mlite/trunk/vhdl/
180	Easily permit full UART simulation	rhoads	6514d 10h	/mlite/trunk/vhdl/
139	Major changes -- updated to Plasma Version 3	rhoads	6828d 06h	/mlite/trunk/vhdl/
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7308d 04h	/mlite/trunk/vhdl/