URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 334

Rev	Log message	Author	Age	Path
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5730d 07h	/mlite/trunk/vhdl/
333	Updated Altera lpm_ram_dp usage for Cyclone FPGAs	rhoads	5730d 07h	/mlite/trunk/vhdl/
332	Updated Altera lpm_ram_dp	rhoads	5730d 07h	/mlite/trunk/vhdl/
331	Commented out unconnected signals	rhoads	5791d 07h	/mlite/trunk/vhdl/
329	Fix interrupt line comment	rhoads	5882d 06h	/mlite/trunk/vhdl/
288	Added Ethernet MAC with DMA	rhoads	6009d 05h	/mlite/trunk/vhdl/
287	Added ethernet and flash control	rhoads	6009d 05h	/mlite/trunk/vhdl/
286	Added eth_dma	rhoads	6009d 05h	/mlite/trunk/vhdl/
285	Added eth_dma	rhoads	6009d 07h	/mlite/trunk/vhdl/
284	Removed unsupported branch likely opcodes	rhoads	6009d 07h	/mlite/trunk/vhdl/
280	Fix comment	rhoads	6026d 05h	/mlite/trunk/vhdl/
279	Expand read buffer size to two characters	rhoads	6026d 05h	/mlite/trunk/vhdl/
278	Fix refresh bug	rhoads	6026d 05h	/mlite/trunk/vhdl/
273	For DDR support	rhoads	6047d 18h	/mlite/trunk/vhdl/
265	Changed write_byte_enable to byte_we	rhoads	6052d 15h	/mlite/trunk/vhdl/
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6052d 15h	/mlite/trunk/vhdl/
263	Changed write_byte_enable to byte_we	rhoads	6052d 15h	/mlite/trunk/vhdl/
262	Changed comment	rhoads	6052d 15h	/mlite/trunk/vhdl/
261	Removed commented out lines	rhoads	6052d 15h	/mlite/trunk/vhdl/
260	Removed Xilinx use statements	rhoads	6052d 15h	/mlite/trunk/vhdl/