URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 347

Rev	Log message	Author	Age	Path
347	Xilinx ISE Project file	rhoads	5621d 02h	/mlite/trunk/vhdl/
346	Support optional 4KB cache	rhoads	5658d 01h	/mlite/trunk/vhdl/
345	Commented out optional mult speedup	rhoads	5661d 22h	/mlite/trunk/vhdl/
344	Fixed compiler warning	rhoads	5661d 22h	/mlite/trunk/vhdl/
343	Initial working cache	rhoads	5661d 22h	/mlite/trunk/vhdl/
337	Initial attempt at a cache	rhoads	5667d 02h	/mlite/trunk/vhdl/
335	Use enable signal for byte_we	rhoads	5708d 20h	/mlite/trunk/vhdl/
334	Short time for averaging read signal for 12.5 MHz case	rhoads	5718d 20h	/mlite/trunk/vhdl/
333	Updated Altera lpm_ram_dp usage for Cyclone FPGAs	rhoads	5718d 20h	/mlite/trunk/vhdl/
332	Updated Altera lpm_ram_dp	rhoads	5718d 20h	/mlite/trunk/vhdl/
331	Commented out unconnected signals	rhoads	5779d 20h	/mlite/trunk/vhdl/
329	Fix interrupt line comment	rhoads	5870d 19h	/mlite/trunk/vhdl/
288	Added Ethernet MAC with DMA	rhoads	5997d 18h	/mlite/trunk/vhdl/
287	Added ethernet and flash control	rhoads	5997d 18h	/mlite/trunk/vhdl/
286	Added eth_dma	rhoads	5997d 18h	/mlite/trunk/vhdl/
285	Added eth_dma	rhoads	5997d 20h	/mlite/trunk/vhdl/
284	Removed unsupported branch likely opcodes	rhoads	5997d 20h	/mlite/trunk/vhdl/
280	Fix comment	rhoads	6014d 18h	/mlite/trunk/vhdl/
279	Expand read buffer size to two characters	rhoads	6014d 18h	/mlite/trunk/vhdl/
278	Fix refresh bug	rhoads	6014d 18h	/mlite/trunk/vhdl/