URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 49

Rev	Log message	Author	Age	Path
49	Fix pause while writting	rhoads	8058d 03h	/mlite/trunk/vhdl/
48	Altera	rhoads	8058d 03h	/mlite/trunk/vhdl/
47	Altera	rhoads	8065d 04h	/mlite/trunk/vhdl/
46	Comments cleanup	rhoads	8065d 05h	/mlite/trunk/vhdl/
45	Fixed signed 64-bit multiply	rhoads	8142d 17h	/mlite/trunk/vhdl/
44	Fixed signed 64-bit multiply	rhoads	8142d 17h	/mlite/trunk/vhdl/
43	Renamed M-lite to Plasma	rhoads	8145d 04h	/mlite/trunk/vhdl/
41	Changed name to M-lite to avoid trademark issues.	rhoads	8177d 09h	/mlite/trunk/vhdl/
40	Added comments	rhoads	8177d 10h	/mlite/trunk/vhdl/
39	Changed name to M-lite to avoid trademark issues.	rhoads	8177d 10h	/mlite/trunk/vhdl/
25	opcodes target	rhoads	8202d 03h	/mlite/trunk/vhdl/
24	Disable interrupts upon reset.	rhoads	8202d 03h	/mlite/trunk/vhdl/
23	Fixed div -x/y.	rhoads	8202d 03h	/mlite/trunk/vhdl/
19	Changed simili run to 40us.	rhoads	8204d 03h	/mlite/trunk/vhdl/
18	Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0.	rhoads	8204d 03h	/mlite/trunk/vhdl/
17	Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces.	rhoads	8204d 03h	/mlite/trunk/vhdl/
13	Removed reg_bank configuration control	rhoads	8208d 03h	/mlite/trunk/vhdl/
12	Better support for dual-port memories, removed old method	rhoads	8208d 03h	/mlite/trunk/vhdl/
11	Added comment for DEBUG mode	rhoads	8208d 03h	/mlite/trunk/vhdl/
10	Add pause_in to process dependency, fixes "lw $4,0($4)"	rhoads	8208d 03h	/mlite/trunk/vhdl/