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[/] [mlite/] [trunk/] [vhdl/] - Rev 72

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Rev Log message Author Age Path
72 accurate_timing, cleanup, pipeline rhoads 8049d 08h /mlite/trunk/vhdl/
71 removed pause in rhoads 8049d 08h /mlite/trunk/vhdl/
70 pipeline rhoads 8049d 08h /mlite/trunk/vhdl/
69 Added a third pipeline stage rhoads 8049d 08h /mlite/trunk/vhdl/
64 Altera rhoads 8057d 13h /mlite/trunk/vhdl/
63 From count.c rhoads 8057d 13h /mlite/trunk/vhdl/
62 updated LPM functions; mem_none->mem_fetch rhoads 8057d 13h /mlite/trunk/vhdl/
61 mem_none -> mem_fetch rhoads 8057d 13h /mlite/trunk/vhdl/
60 reset control rhoads 8057d 13h /mlite/trunk/vhdl/
59 Ascyn reset rhoads 8057d 13h /mlite/trunk/vhdl/
58 Altera rhoads 8057d 13h /mlite/trunk/vhdl/
57 Interface to Altera FPGA rhoads 8057d 13h /mlite/trunk/vhdl/
56 Altera, added byte_sel_reg for tigher timing and avoid possible glitches rhoads 8057d 13h /mlite/trunk/vhdl/
55 Altera rhoads 8057d 13h /mlite/trunk/vhdl/
51 GENERIC rhoads 8068d 08h /mlite/trunk/vhdl/
50 Update prototypes rhoads 8068d 08h /mlite/trunk/vhdl/
49 Fix pause while writting rhoads 8068d 08h /mlite/trunk/vhdl/
48 Altera rhoads 8068d 08h /mlite/trunk/vhdl/
47 Altera rhoads 8075d 09h /mlite/trunk/vhdl/
46 Comments cleanup rhoads 8075d 09h /mlite/trunk/vhdl/

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