URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] - Rev 82

Rev	Log message	Author	Age	Path
82	Added to process list	rhoads	8168d 10h	/mlite/trunk/vhdl/
81	Removed unused case statements	rhoads	8168d 10h	/mlite/trunk/vhdl/
79	pipeline	rhoads	8176d 11h	/mlite/trunk/vhdl/
76	better pause for pipeline	rhoads	8176d 11h	/mlite/trunk/vhdl/
75	cleanup	rhoads	8176d 11h	/mlite/trunk/vhdl/
74	pause in	rhoads	8176d 11h	/mlite/trunk/vhdl/
73	pipeline, better reset	rhoads	8176d 11h	/mlite/trunk/vhdl/
72	accurate_timing, cleanup, pipeline	rhoads	8176d 11h	/mlite/trunk/vhdl/
71	removed pause in	rhoads	8176d 11h	/mlite/trunk/vhdl/
70	pipeline	rhoads	8176d 11h	/mlite/trunk/vhdl/
69	Added a third pipeline stage	rhoads	8176d 11h	/mlite/trunk/vhdl/
64	Altera	rhoads	8184d 16h	/mlite/trunk/vhdl/
63	From count.c	rhoads	8184d 16h	/mlite/trunk/vhdl/
62	updated LPM functions; mem_none->mem_fetch	rhoads	8184d 16h	/mlite/trunk/vhdl/
61	mem_none -> mem_fetch	rhoads	8184d 16h	/mlite/trunk/vhdl/
60	reset control	rhoads	8184d 16h	/mlite/trunk/vhdl/
59	Ascyn reset	rhoads	8184d 16h	/mlite/trunk/vhdl/
58	Altera	rhoads	8184d 16h	/mlite/trunk/vhdl/
57	Interface to Altera FPGA	rhoads	8184d 16h	/mlite/trunk/vhdl/
56	Altera, added byte_sel_reg for tigher timing and avoid possible glitches	rhoads	8184d 16h	/mlite/trunk/vhdl/