OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
57 new fifo design, is now generic (verified with altera and xilinx) and uses block ram JonasDC 4128d 09h /mod_sim_exp/
56 this is a branch to test performance of a new style of ram JonasDC 4128d 12h /mod_sim_exp/
55 updated resource usage in comments JonasDC 4129d 08h /mod_sim_exp/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4129d 08h /mod_sim_exp/
53 correctly inferred ram for altera dual port ram JonasDC 4129d 15h /mod_sim_exp/
52 correct inferring of blockram, no additional resources. JonasDC 4129d 16h /mod_sim_exp/
51 true dual port ram for xilinx JonasDC 4129d 16h /mod_sim_exp/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4129d 16h /mod_sim_exp/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.		 JonasDC 4141d 11h /mod_sim_exp/
48 Tag of the starting version of the project JonasDC 4141d 11h /mod_sim_exp/
47 added documentation for the IP core. JonasDC 4209d 16h /mod_sim_exp/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4209d 16h /mod_sim_exp/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4209d 16h /mod_sim_exp/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4213d 10h /mod_sim_exp/
43 made the core parameters generics JonasDC 4213d 10h /mod_sim_exp/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4219d 18h /mod_sim_exp/
41 removed deprecated files from version control JonasDC 4219d 18h /mod_sim_exp/
40 adjusted core instantiation to new core module name JonasDC 4227d 22h /mod_sim_exp/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4228d 09h /mod_sim_exp/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4228d 14h /mod_sim_exp/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.