Rev |
Log message |
Author |
Age |
Path |
80 |
renamed to version 1.1 to follow the versioning system |
JonasDC |
4159d 09h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
49 |
First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives. |
JonasDC |
4199d 10h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4267d 15h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
43 |
made the core parameters generics |
JonasDC |
4271d 08h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
41 |
removed deprecated files from version control |
JonasDC |
4277d 16h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4286d 07h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4286d 13h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4290d 10h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4291d 06h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4291d 09h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4291d 12h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4291d 13h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4291d 18h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4291d 19h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4292d 09h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4295d 18h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
23 |
added descriptive comments |
JonasDC |
4295d 19h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4298d 13h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
21 |
changed x_i signal to xi |
JonasDC |
4299d 20h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4299d 20h |
/mod_sim_exp/tags/Release_1.1/rtl/vhdl/core/ |