URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [interface/] - Rev 100

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4093d 21h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4133d 22h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4202d 03h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4205d 20h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
43	made the core parameters generics	JonasDC	4205d 20h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4212d 04h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
40	adjusted core instantiation to new core module name	JonasDC	4220d 08h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4246d 03h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/