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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sim/] [src/] - Rev 98

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80 renamed to version 1.1 to follow the versioning system JonasDC 4106d 00h /mod_sim_exp/tags/Release_1.1/sim/src/
49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4146d 01h /mod_sim_exp/tags/Release_1.1/sim/src/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4238d 00h /mod_sim_exp/tags/Release_1.1/sim/src/
27 test input values for multiplier_tb JonasDC 4239d 00h /mod_sim_exp/tags/Release_1.1/sim/src/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4254d 01h /mod_sim_exp/tags/Release_1.1/sim/src/

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