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[/] [mod_sim_exp/] [tags/] [Release_1.3/] - Rev 12

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Rev Log message Author Age Path
12 updated comments, file is now completely according to design rules JonasDC 4309d 16h /mod_sim_exp/tags/Release_1.3/
11 simulation output folder JonasDC 4309d 18h /mod_sim_exp/tags/Release_1.3/
10 changed signal input port names to correct name JonasDC 4309d 21h /mod_sim_exp/tags/Release_1.3/
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names		 JonasDC 4309d 21h /mod_sim_exp/tags/Release_1.3/
8 added descriptive comments JonasDC 4309d 23h /mod_sim_exp/tags/Release_1.3/
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4309d 23h /mod_sim_exp/tags/Release_1.3/
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4309d 23h /mod_sim_exp/tags/Release_1.3/
5 not needed on svn, is generated by testbench JonasDC 4310d 00h /mod_sim_exp/tags/Release_1.3/
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4310d 01h /mod_sim_exp/tags/Release_1.3/
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4310d 15h /mod_sim_exp/tags/Release_1.3/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4314d 21h /mod_sim_exp/tags/Release_1.3/
1 The project and the structure was created root 4316d 21h /mod_sim_exp/tags/Release_1.3/

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