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[/] [mod_sim_exp/] [tags/] [Release_1.3/] - Rev 32

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32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4287d 16h /mod_sim_exp/tags/Release_1.3/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4287d 21h /mod_sim_exp/tags/Release_1.3/
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4287d 22h /mod_sim_exp/tags/Release_1.3/
29 added software for generation of test input for the tesbenches JonasDC 4288d 11h /mod_sim_exp/tags/Release_1.3/
28 updated makefile for new pipeline sources JonasDC 4288d 12h /mod_sim_exp/tags/Release_1.3/
27 test input values for multiplier_tb JonasDC 4288d 12h /mod_sim_exp/tags/Release_1.3/
26 testbench for only the montgommery multiplier JonasDC 4288d 12h /mod_sim_exp/tags/Release_1.3/
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4288d 12h /mod_sim_exp/tags/Release_1.3/
24 changed names of top-level module to mod_sim_exp_core JonasDC 4291d 21h /mod_sim_exp/tags/Release_1.3/
23 added descriptive comments JonasDC 4291d 22h /mod_sim_exp/tags/Release_1.3/
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4294d 16h /mod_sim_exp/tags/Release_1.3/
21 changed x_i signal to xi JonasDC 4295d 23h /mod_sim_exp/tags/Release_1.3/
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4295d 23h /mod_sim_exp/tags/Release_1.3/
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4300d 18h /mod_sim_exp/tags/Release_1.3/
18 updated stages with comments and renamed some signals for consistency JonasDC 4301d 18h /mod_sim_exp/tags/Release_1.3/
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4301d 23h /mod_sim_exp/tags/Release_1.3/
16 package with modified generic parameter for register_n JonasDC 4302d 12h /mod_sim_exp/tags/Release_1.3/
15 changed generic for register width from n to width for consistency JonasDC 4302d 12h /mod_sim_exp/tags/Release_1.3/
14 changed comments, file is now according to OC design rules JonasDC 4302d 13h /mod_sim_exp/tags/Release_1.3/
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4302d 13h /mod_sim_exp/tags/Release_1.3/

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