URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [bench/] [vhdl/] - Rev 91

Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4096d 02h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
76	testbench update	JonasDC	4104d 11h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4109d 06h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4204d 08h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
43	made the core parameters generics	JonasDC	4208d 01h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4227d 03h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
26	testbench for only the montgommery multiplier	JonasDC	4229d 02h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4232d 11h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4244d 02h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4248d 08h	/mod_sim_exp/tags/Release_1.3/bench/vhdl/