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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] - Rev 65

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Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4152d 20h	/mod_sim_exp/tags/Release_1.3/rtl/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4153d 01h	/mod_sim_exp/tags/Release_1.3/rtl/
62	not used anymore	JonasDC	4153d 04h	/mod_sim_exp/tags/Release_1.3/rtl/
61	updated comments, added optional altera constraint	JonasDC	4153d 04h	/mod_sim_exp/tags/Release_1.3/rtl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4155d 18h	/mod_sim_exp/tags/Release_1.3/rtl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4155d 19h	/mod_sim_exp/tags/Release_1.3/rtl/
55	updated resource usage in comments	JonasDC	4159d 18h	/mod_sim_exp/tags/Release_1.3/rtl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4159d 18h	/mod_sim_exp/tags/Release_1.3/rtl/
53	correctly inferred ram for altera dual port ram	JonasDC	4160d 01h	/mod_sim_exp/tags/Release_1.3/rtl/
52	correct inferring of blockram, no additional resources.	JonasDC	4160d 01h	/mod_sim_exp/tags/Release_1.3/rtl/
51	true dual port ram for xilinx	JonasDC	4160d 02h	/mod_sim_exp/tags/Release_1.3/rtl/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4160d 02h	/mod_sim_exp/tags/Release_1.3/rtl/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4240d 02h	/mod_sim_exp/tags/Release_1.3/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4243d 20h	/mod_sim_exp/tags/Release_1.3/rtl/
43	made the core parameters generics	JonasDC	4243d 20h	/mod_sim_exp/tags/Release_1.3/rtl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4250d 03h	/mod_sim_exp/tags/Release_1.3/rtl/
41	removed deprecated files from version control	JonasDC	4250d 03h	/mod_sim_exp/tags/Release_1.3/rtl/
40	adjusted core instantiation to new core module name	JonasDC	4258d 07h	/mod_sim_exp/tags/Release_1.3/rtl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4258d 19h	/mod_sim_exp/tags/Release_1.3/rtl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4259d 00h	/mod_sim_exp/tags/Release_1.3/rtl/

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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] - Rev 65

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