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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] - Rev 55

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Rev Log message Author Age Path
55 updated resource usage in comments JonasDC 4120d 21h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4120d 21h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
53 correctly inferred ram for altera dual port ram JonasDC 4121d 04h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
52 correct inferring of blockram, no additional resources. JonasDC 4121d 04h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
51 true dual port ram for xilinx JonasDC 4121d 05h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4121d 05h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4201d 05h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4204d 22h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
43 made the core parameters generics JonasDC 4204d 22h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4211d 06h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
41 removed deprecated files from version control JonasDC 4211d 06h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
40 adjusted core instantiation to new core module name JonasDC 4219d 10h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4219d 22h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4220d 03h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4224d 00h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4224d 20h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4225d 00h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4225d 03h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4225d 04h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4225d 09h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/

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