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[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] [interface/] - Rev 92

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Rev Log message Author Age Path
79 Tag for version 1.3 (with new ram style JonasDC 4118d 21h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
77 found fault in code, now synthesizes normally JonasDC 4124d 19h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
74 removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. JonasDC 4130d 02h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
73 updated plb interface, mem_style and device generics added JonasDC 4131d 01h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4139d 20h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4227d 03h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4230d 20h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
43 made the core parameters generics JonasDC 4230d 20h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4237d 04h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
40 adjusted core instantiation to new core module name JonasDC 4245d 08h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4271d 03h /mod_sim_exp/tags/Release_1.3/rtl/vhdl/interface/

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