URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl/] [vhdl/] [ram/] - Rev 92

Rev	Log message	Author	Age	Path
79	Tag for version 1.3 (with new ram style	JonasDC	4118d 21h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4132d 04h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
62	not used anymore	JonasDC	4140d 04h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
61	updated comments, added optional altera constraint	JonasDC	4140d 04h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4142d 19h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4142d 19h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
53	correctly inferred ram for altera dual port ram	JonasDC	4147d 02h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
52	correct inferring of blockram, no additional resources.	JonasDC	4147d 02h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
51	true dual port ram for xilinx	JonasDC	4147d 03h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4147d 03h	/mod_sim_exp/tags/Release_1.3/rtl/vhdl/ram/