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[/] [mod_sim_exp/] [tags/] [Release_1.4/] - Rev 85

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Rev	Log message	Author	Age	Path
85	changed so that reset now also affects slave register	JonasDC	4090d 02h	/mod_sim_exp/tags/Release_1.4/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4091d 11h	/mod_sim_exp/tags/Release_1.4/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4093d 11h	/mod_sim_exp/tags/Release_1.4/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4110d 07h	/mod_sim_exp/tags/Release_1.4/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4110d 07h	/mod_sim_exp/tags/Release_1.4/
78	updated documentation with new RAM style information	JonasDC	4120d 01h	/mod_sim_exp/tags/Release_1.4/
77	found fault in code, now synthesizes normally	JonasDC	4125d 23h	/mod_sim_exp/tags/Release_1.4/
76	testbench update	JonasDC	4128d 10h	/mod_sim_exp/tags/Release_1.4/
75	made rw_address a vector of a fixed width	JonasDC	4128d 10h	/mod_sim_exp/tags/Release_1.4/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4131d 06h	/mod_sim_exp/tags/Release_1.4/
73	updated plb interface, mem_style and device generics added	JonasDC	4132d 05h	/mod_sim_exp/tags/Release_1.4/
72	deleted old resources	JonasDC	4133d 05h	/mod_sim_exp/tags/Release_1.4/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4133d 05h	/mod_sim_exp/tags/Release_1.4/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4133d 05h	/mod_sim_exp/tags/Release_1.4/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4133d 05h	/mod_sim_exp/tags/Release_1.4/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4133d 08h	/mod_sim_exp/tags/Release_1.4/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4133d 09h	/mod_sim_exp/tags/Release_1.4/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4141d 00h	/mod_sim_exp/tags/Release_1.4/
64	added synthesis reports of xilinx and altera	JonasDC	4141d 06h	/mod_sim_exp/tags/Release_1.4/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4141d 06h	/mod_sim_exp/tags/Release_1.4/

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[/] [mod_sim_exp/] [tags/] [Release_1.4/] - Rev 85

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