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[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] - Rev 45

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Rev	Log message	Author	Age	Path
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4200d 20h	/mod_sim_exp/tags/Release_1.4/rtl/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4204d 14h	/mod_sim_exp/tags/Release_1.4/rtl/
43	made the core parameters generics	JonasDC	4204d 14h	/mod_sim_exp/tags/Release_1.4/rtl/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4210d 22h	/mod_sim_exp/tags/Release_1.4/rtl/
41	removed deprecated files from version control	JonasDC	4210d 22h	/mod_sim_exp/tags/Release_1.4/rtl/
40	adjusted core instantiation to new core module name	JonasDC	4219d 02h	/mod_sim_exp/tags/Release_1.4/rtl/
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4219d 13h	/mod_sim_exp/tags/Release_1.4/rtl/
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4219d 19h	/mod_sim_exp/tags/Release_1.4/rtl/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4223d 16h	/mod_sim_exp/tags/Release_1.4/rtl/
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4224d 12h	/mod_sim_exp/tags/Release_1.4/rtl/
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4224d 15h	/mod_sim_exp/tags/Release_1.4/rtl/
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4224d 18h	/mod_sim_exp/tags/Release_1.4/rtl/
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4224d 19h	/mod_sim_exp/tags/Release_1.4/rtl/
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4225d 00h	/mod_sim_exp/tags/Release_1.4/rtl/
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4225d 01h	/mod_sim_exp/tags/Release_1.4/rtl/
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4225d 15h	/mod_sim_exp/tags/Release_1.4/rtl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4229d 00h	/mod_sim_exp/tags/Release_1.4/rtl/
23	added descriptive comments	JonasDC	4229d 01h	/mod_sim_exp/tags/Release_1.4/rtl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4231d 18h	/mod_sim_exp/tags/Release_1.4/rtl/
21	changed x_i signal to xi	JonasDC	4233d 02h	/mod_sim_exp/tags/Release_1.4/rtl/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.4/] [rtl/] - Rev 45

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