| Rev |
Log message |
Author |
Age |
Path |
| 65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4171d 01h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4171d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 62 |
not used anymore |
JonasDC |
4171d 09h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 61 |
updated comments, added optional altera constraint |
JonasDC |
4171d 09h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4174d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4174d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 55 |
updated resource usage in comments |
JonasDC |
4177d 23h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4178d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4178d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4178d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 51 |
true dual port ram for xilinx |
JonasDC |
4178d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4178d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4258d 07h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4262d 01h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 43 |
made the core parameters generics |
JonasDC |
4262d 01h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4268d 09h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 41 |
removed deprecated files from version control |
JonasDC |
4268d 09h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 40 |
adjusted core instantiation to new core module name |
JonasDC |
4276d 13h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4277d 00h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
| 38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4277d 06h |
/mod_sim_exp/tags/Release_1.4/rtl/vhdl/ |
