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[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] - Rev 84

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Rev	Log message	Author	Age	Path
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4091d 07h	/mod_sim_exp/tags/Release_1.5/rtl/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4093d 08h	/mod_sim_exp/tags/Release_1.5/rtl/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4110d 04h	/mod_sim_exp/tags/Release_1.5/rtl/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4110d 04h	/mod_sim_exp/tags/Release_1.5/rtl/
77	found fault in code, now synthesizes normally	JonasDC	4125d 19h	/mod_sim_exp/tags/Release_1.5/rtl/
75	made rw_address a vector of a fixed width	JonasDC	4128d 06h	/mod_sim_exp/tags/Release_1.5/rtl/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4131d 02h	/mod_sim_exp/tags/Release_1.5/rtl/
73	updated plb interface, mem_style and device generics added	JonasDC	4132d 01h	/mod_sim_exp/tags/Release_1.5/rtl/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4133d 02h	/mod_sim_exp/tags/Release_1.5/rtl/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4133d 05h	/mod_sim_exp/tags/Release_1.5/rtl/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4133d 05h	/mod_sim_exp/tags/Release_1.5/rtl/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4140d 21h	/mod_sim_exp/tags/Release_1.5/rtl/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4141d 02h	/mod_sim_exp/tags/Release_1.5/rtl/
62	not used anymore	JonasDC	4141d 05h	/mod_sim_exp/tags/Release_1.5/rtl/
61	updated comments, added optional altera constraint	JonasDC	4141d 05h	/mod_sim_exp/tags/Release_1.5/rtl/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4143d 19h	/mod_sim_exp/tags/Release_1.5/rtl/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4143d 20h	/mod_sim_exp/tags/Release_1.5/rtl/
55	updated resource usage in comments	JonasDC	4147d 19h	/mod_sim_exp/tags/Release_1.5/rtl/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4147d 19h	/mod_sim_exp/tags/Release_1.5/rtl/
53	correctly inferred ram for altera dual port ram	JonasDC	4148d 02h	/mod_sim_exp/tags/Release_1.5/rtl/

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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] - Rev 84

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