OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 57

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
55 updated resource usage in comments JonasDC 4125d 21h /mod_sim_exp/trunk/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4125d 21h /mod_sim_exp/trunk/
53 correctly inferred ram for altera dual port ram JonasDC 4126d 04h /mod_sim_exp/trunk/
52 correct inferring of blockram, no additional resources. JonasDC 4126d 04h /mod_sim_exp/trunk/
51 true dual port ram for xilinx JonasDC 4126d 05h /mod_sim_exp/trunk/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4126d 05h /mod_sim_exp/trunk/
47 added documentation for the IP core. JonasDC 4206d 05h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4206d 05h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4206d 05h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4209d 23h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4209d 23h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4216d 06h /mod_sim_exp/trunk/
41 removed deprecated files from version control JonasDC 4216d 07h /mod_sim_exp/trunk/
40 adjusted core instantiation to new core module name JonasDC 4224d 11h /mod_sim_exp/trunk/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4224d 22h /mod_sim_exp/trunk/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4225d 03h /mod_sim_exp/trunk/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4229d 00h /mod_sim_exp/trunk/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4229d 20h /mod_sim_exp/trunk/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4229d 23h /mod_sim_exp/trunk/
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4230d 00h /mod_sim_exp/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.