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[/] [mod_sim_exp/] [trunk/] - Rev 59

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Rev Log message Author Age Path
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)		 JonasDC 4246d 13h /mod_sim_exp/trunk/
55 updated resource usage in comments JonasDC 4250d 12h /mod_sim_exp/trunk/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4250d 12h /mod_sim_exp/trunk/
53 correctly inferred ram for altera dual port ram JonasDC 4250d 19h /mod_sim_exp/trunk/
52 correct inferring of blockram, no additional resources. JonasDC 4250d 19h /mod_sim_exp/trunk/
51 true dual port ram for xilinx JonasDC 4250d 20h /mod_sim_exp/trunk/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4250d 20h /mod_sim_exp/trunk/
47 added documentation for the IP core. JonasDC 4330d 20h /mod_sim_exp/trunk/
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4330d 20h /mod_sim_exp/trunk/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4330d 20h /mod_sim_exp/trunk/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4334d 14h /mod_sim_exp/trunk/
43 made the core parameters generics JonasDC 4334d 14h /mod_sim_exp/trunk/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4340d 21h /mod_sim_exp/trunk/
41 removed deprecated files from version control JonasDC 4340d 22h /mod_sim_exp/trunk/
40 adjusted core instantiation to new core module name JonasDC 4349d 02h /mod_sim_exp/trunk/
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4349d 13h /mod_sim_exp/trunk/
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4349d 18h /mod_sim_exp/trunk/
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4353d 15h /mod_sim_exp/trunk/
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4354d 11h /mod_sim_exp/trunk/
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes		 JonasDC 4354d 14h /mod_sim_exp/trunk/

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