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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] - Rev 90

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Rev	Log message	Author	Age	Path
90	reverted changes from previous revision, updated AXI version with testbench	JonasDC	4023d 18h	/mod_sim_exp/trunk/
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4087d 16h	/mod_sim_exp/trunk/
88	small update on documentation, changed fault in axi control_reg	JonasDC	4093d 17h	/mod_sim_exp/trunk/
87	updated documentation to version 1.4 core now supports the AXI4-Lite bus	JonasDC	4093d 18h	/mod_sim_exp/trunk/
86	update on previous	JonasDC	4093d 18h	/mod_sim_exp/trunk/
85	changed so that reset now also affects slave register	JonasDC	4093d 18h	/mod_sim_exp/trunk/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4095d 03h	/mod_sim_exp/trunk/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4097d 03h	/mod_sim_exp/trunk/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4114d 00h	/mod_sim_exp/trunk/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4114d 00h	/mod_sim_exp/trunk/
78	updated documentation with new RAM style information	JonasDC	4123d 18h	/mod_sim_exp/trunk/
77	found fault in code, now synthesizes normally	JonasDC	4129d 15h	/mod_sim_exp/trunk/
76	testbench update	JonasDC	4132d 02h	/mod_sim_exp/trunk/
75	made rw_address a vector of a fixed width	JonasDC	4132d 02h	/mod_sim_exp/trunk/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4134d 22h	/mod_sim_exp/trunk/
73	updated plb interface, mem_style and device generics added	JonasDC	4135d 21h	/mod_sim_exp/trunk/
72	deleted old resources	JonasDC	4136d 21h	/mod_sim_exp/trunk/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4136d 21h	/mod_sim_exp/trunk/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4136d 21h	/mod_sim_exp/trunk/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4136d 21h	/mod_sim_exp/trunk/

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[/] [mod_sim_exp/] [trunk/] - Rev 90

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