URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] - Rev 56

Rev	Log message	Author	Age	Path
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4201d 18h	/mod_sim_exp/trunk/bench/
43	made the core parameters generics	JonasDC	4205d 12h	/mod_sim_exp/trunk/bench/
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4224d 14h	/mod_sim_exp/trunk/bench/
26	testbench for only the montgommery multiplier	JonasDC	4226d 13h	/mod_sim_exp/trunk/bench/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4229d 22h	/mod_sim_exp/trunk/bench/
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4241d 13h	/mod_sim_exp/trunk/bench/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4245d 19h	/mod_sim_exp/trunk/bench/