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[/] [mod_sim_exp/] [trunk/] [rtl/] - Rev 67

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67 added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. JonasDC 4110d 02h /mod_sim_exp/trunk/rtl/
66 added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools.		 JonasDC 4110d 02h /mod_sim_exp/trunk/rtl/
65 updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package		 JonasDC 4117d 18h /mod_sim_exp/trunk/rtl/
63 now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx JonasDC 4118d 00h /mod_sim_exp/trunk/rtl/
62 not used anymore JonasDC 4118d 02h /mod_sim_exp/trunk/rtl/
61 updated comments, added optional altera constraint JonasDC 4118d 02h /mod_sim_exp/trunk/rtl/
60 generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates.		 JonasDC 4120d 17h /mod_sim_exp/trunk/rtl/
59 added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates)		 JonasDC 4120d 17h /mod_sim_exp/trunk/rtl/
55 updated resource usage in comments JonasDC 4124d 17h /mod_sim_exp/trunk/rtl/
54 generic fifo design: correctrly inferred by xilinx and altera JonasDC 4124d 17h /mod_sim_exp/trunk/rtl/
53 correctly inferred ram for altera dual port ram JonasDC 4124d 23h /mod_sim_exp/trunk/rtl/
52 correct inferring of blockram, no additional resources. JonasDC 4125d 00h /mod_sim_exp/trunk/rtl/
51 true dual port ram for xilinx JonasDC 4125d 00h /mod_sim_exp/trunk/rtl/
50 added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx		 JonasDC 4125d 01h /mod_sim_exp/trunk/rtl/
45 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4205d 00h /mod_sim_exp/trunk/rtl/
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4208d 18h /mod_sim_exp/trunk/rtl/
43 made the core parameters generics JonasDC 4208d 18h /mod_sim_exp/trunk/rtl/
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4215d 02h /mod_sim_exp/trunk/rtl/
41 removed deprecated files from version control JonasDC 4215d 02h /mod_sim_exp/trunk/rtl/
40 adjusted core instantiation to new core module name JonasDC 4223d 06h /mod_sim_exp/trunk/rtl/

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