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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 25

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Rev	Log message	Author	Age	Path
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4380d 04h	/mod_sim_exp/trunk/rtl/vhdl/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4383d 13h	/mod_sim_exp/trunk/rtl/vhdl/
23	added descriptive comments	JonasDC	4383d 15h	/mod_sim_exp/trunk/rtl/vhdl/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4386d 08h	/mod_sim_exp/trunk/rtl/vhdl/
21	changed x_i signal to xi	JonasDC	4387d 16h	/mod_sim_exp/trunk/rtl/vhdl/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4387d 16h	/mod_sim_exp/trunk/rtl/vhdl/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4392d 11h	/mod_sim_exp/trunk/rtl/vhdl/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4393d 11h	/mod_sim_exp/trunk/rtl/vhdl/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4393d 16h	/mod_sim_exp/trunk/rtl/vhdl/
16	package with modified generic parameter for register_n	JonasDC	4394d 05h	/mod_sim_exp/trunk/rtl/vhdl/
15	changed generic for register width from n to width for consistency	JonasDC	4394d 05h	/mod_sim_exp/trunk/rtl/vhdl/
14	changed comments, file is now according to OC design rules	JonasDC	4394d 05h	/mod_sim_exp/trunk/rtl/vhdl/
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4394d 05h	/mod_sim_exp/trunk/rtl/vhdl/
12	updated comments, file is now completely according to design rules	JonasDC	4394d 05h	/mod_sim_exp/trunk/rtl/vhdl/
10	changed signal input port names to correct name	JonasDC	4394d 10h	/mod_sim_exp/trunk/rtl/vhdl/
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4394d 10h	/mod_sim_exp/trunk/rtl/vhdl/
8	added descriptive comments	JonasDC	4394d 13h	/mod_sim_exp/trunk/rtl/vhdl/
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4394d 13h	/mod_sim_exp/trunk/rtl/vhdl/
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4394d 13h	/mod_sim_exp/trunk/rtl/vhdl/
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4394d 15h	/mod_sim_exp/trunk/rtl/vhdl/

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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 25

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