Rev |
Log message |
Author |
Age |
Path |
85 |
changed so that reset now also affects slave register |
JonasDC |
4147d 15h |
/mod_sim_exp/trunk/rtl/vhdl/ |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4148d 23h |
/mod_sim_exp/trunk/rtl/vhdl/ |
83 |
now using values from mod_sim_exp_pkg instead of direct entity |
JonasDC |
4151d 00h |
/mod_sim_exp/trunk/rtl/vhdl/ |
82 |
added first version of axi-lite interface and testbench for basic axi-lite operations, now under test |
JonasDC |
4167d 20h |
/mod_sim_exp/trunk/rtl/vhdl/ |
81 |
updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration |
JonasDC |
4167d 20h |
/mod_sim_exp/trunk/rtl/vhdl/ |
77 |
found fault in code, now synthesizes normally |
JonasDC |
4183d 12h |
/mod_sim_exp/trunk/rtl/vhdl/ |
75 |
made rw_address a vector of a fixed width |
JonasDC |
4185d 23h |
/mod_sim_exp/trunk/rtl/vhdl/ |
74 |
removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented. |
JonasDC |
4188d 19h |
/mod_sim_exp/trunk/rtl/vhdl/ |
73 |
updated plb interface, mem_style and device generics added |
JonasDC |
4189d 18h |
/mod_sim_exp/trunk/rtl/vhdl/ |
69 |
big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources. |
JonasDC |
4190d 18h |
/mod_sim_exp/trunk/rtl/vhdl/ |
67 |
added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring. |
JonasDC |
4190d 21h |
/mod_sim_exp/trunk/rtl/vhdl/ |
66 |
added asymmetric ram structures to support a more performant ramstyle.
defined for xilinx and altera, not tested with other tools. |
JonasDC |
4190d 21h |
/mod_sim_exp/trunk/rtl/vhdl/ |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4198d 13h |
/mod_sim_exp/trunk/rtl/vhdl/ |
63 |
now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx |
JonasDC |
4198d 19h |
/mod_sim_exp/trunk/rtl/vhdl/ |
62 |
not used anymore |
JonasDC |
4198d 21h |
/mod_sim_exp/trunk/rtl/vhdl/ |
61 |
updated comments, added optional altera constraint |
JonasDC |
4198d 21h |
/mod_sim_exp/trunk/rtl/vhdl/ |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4201d 12h |
/mod_sim_exp/trunk/rtl/vhdl/ |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4201d 12h |
/mod_sim_exp/trunk/rtl/vhdl/ |
55 |
updated resource usage in comments |
JonasDC |
4205d 12h |
/mod_sim_exp/trunk/rtl/vhdl/ |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4205d 12h |
/mod_sim_exp/trunk/rtl/vhdl/ |