URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 66

Rev	Log message	Author	Age	Path
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4127d 20h	/mod_sim_exp/trunk/rtl/vhdl/interface/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4215d 02h	/mod_sim_exp/trunk/rtl/vhdl/interface/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4218d 19h	/mod_sim_exp/trunk/rtl/vhdl/interface/
43	made the core parameters generics	JonasDC	4218d 19h	/mod_sim_exp/trunk/rtl/vhdl/interface/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4225d 03h	/mod_sim_exp/trunk/rtl/vhdl/interface/
40	adjusted core instantiation to new core module name	JonasDC	4233d 07h	/mod_sim_exp/trunk/rtl/vhdl/interface/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4259d 03h	/mod_sim_exp/trunk/rtl/vhdl/interface/