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URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 89

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Rev	Log message	Author	Age	Path
89	updated vhdl files so now different clock frequencies are posible for the core and bus interface.	JonasDC	4070d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/
86	update on previous	JonasDC	4076d 10h	/mod_sim_exp/trunk/rtl/vhdl/interface/
85	changed so that reset now also affects slave register	JonasDC	4076d 10h	/mod_sim_exp/trunk/rtl/vhdl/interface/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4077d 19h	/mod_sim_exp/trunk/rtl/vhdl/interface/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4096d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/
77	found fault in code, now synthesizes normally	JonasDC	4112d 07h	/mod_sim_exp/trunk/rtl/vhdl/interface/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4117d 14h	/mod_sim_exp/trunk/rtl/vhdl/interface/
73	updated plb interface, mem_style and device generics added	JonasDC	4118d 14h	/mod_sim_exp/trunk/rtl/vhdl/interface/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4127d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4214d 15h	/mod_sim_exp/trunk/rtl/vhdl/interface/
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4218d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/
43	made the core parameters generics	JonasDC	4218d 09h	/mod_sim_exp/trunk/rtl/vhdl/interface/
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4224d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/
40	adjusted core instantiation to new core module name	JonasDC	4232d 21h	/mod_sim_exp/trunk/rtl/vhdl/interface/
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4258d 16h	/mod_sim_exp/trunk/rtl/vhdl/interface/

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