URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sim/] - Rev 16

Rev	Log message	Author	Age	Path
16	minor edits; buck fixes in PMP see changelog in NEORV32.pdf for more information	zero_gravity	1403d 06h	/neorv32/trunk/sim/
15	updated to HW version 1.3.5.0 see changelog in NEORV32.pdf for more information	zero_gravity	1404d 06h	/neorv32/trunk/sim/
14	update to HW version 1.3.0.0 see changelog in NEORV32.pdf for more information	zero_gravity	1408d 11h	/neorv32/trunk/sim/
13	updates, optimizations and bug fixes; see changelog in NEORV32.pdf	zero_gravity	1412d 03h	/neorv32/trunk/sim/
12	Processor version 1.2.0.5 - see changelog in NEORV32.pdf	zero_gravity	1413d 10h	/neorv32/trunk/sim/
11	new hardware version, see changelog in NEORV32.pdf	zero_gravity	1423d 05h	/neorv32/trunk/sim/
8	added missing FENCE instruction; added optional Zifencei CPU extension	zero_gravity	1427d 03h	/neorv32/trunk/sim/
7	removed "mtinst" CSR since it is not ratified yet by the RISC-V specs	zero_gravity	1427d 05h	/neorv32/trunk/sim/
6	new processor version: 1.0.0.0 -> increased performance; debugged errors; processor now passes risc-v compliance tests; see changelog for more information	zero_gravity	1428d 01h	/neorv32/trunk/sim/
4	see NEORV32.pdf for changelog	zero_gravity	1436d 11h	/neorv32/trunk/sim/
3	general updates, see changelog in NEORV32.pdf for more information	zero_gravity	1438d 05h	/neorv32/trunk/sim/
2	- initial commit	zero_gravity	1439d 06h	/neorv32/trunk/sim/