URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [example/] - Rev 17

Rev	Log message	Author	Age	Path
17	minor edits and clean-ups	zero_gravity	1412d 06h	/neorv32/trunk/sw/example/
16	minor edits; buck fixes in PMP see changelog in NEORV32.pdf for more information	zero_gravity	1412d 09h	/neorv32/trunk/sw/example/
15	updated to HW version 1.3.5.0 see changelog in NEORV32.pdf for more information	zero_gravity	1413d 08h	/neorv32/trunk/sw/example/
14	update to HW version 1.3.0.0 see changelog in NEORV32.pdf for more information	zero_gravity	1417d 13h	/neorv32/trunk/sw/example/
13	updates, optimizations and bug fixes; see changelog in NEORV32.pdf	zero_gravity	1421d 06h	/neorv32/trunk/sw/example/
12	Processor version 1.2.0.5 - see changelog in NEORV32.pdf	zero_gravity	1422d 12h	/neorv32/trunk/sw/example/
11	new hardware version, see changelog in NEORV32.pdf	zero_gravity	1432d 07h	/neorv32/trunk/sw/example/
8	added missing FENCE instruction; added optional Zifencei CPU extension	zero_gravity	1436d 06h	/neorv32/trunk/sw/example/
7	removed "mtinst" CSR since it is not ratified yet by the RISC-V specs	zero_gravity	1436d 08h	/neorv32/trunk/sw/example/
6	new processor version: 1.0.0.0 -> increased performance; debugged errors; processor now passes risc-v compliance tests; see changelog for more information	zero_gravity	1437d 04h	/neorv32/trunk/sw/example/
3	general updates, see changelog in NEORV32.pdf for more information	zero_gravity	1447d 07h	/neorv32/trunk/sw/example/
2	- initial commit	zero_gravity	1448d 08h	/neorv32/trunk/sw/example/