URL https://opencores.org/ocsvn/next186/next186/trunk

Subversion Repositories next186

[/] [next186/] - Rev 20

Rev	Log message	Author	Age	Path
20	Implemented the undocumented SALC instructions (SBB AL, AL without affecting the flags) Some speed improvements (separate data/address I/O path)	ndumitrache	2454d 04h	/next186/
19	Add A20 address line	ndumitrache	3675d 01h	/next186/
18	nicer code	ndumitrache	3977d 19h	/next186/
17	fixed OV/CY flags for IMUL	ndumitrache	3986d 02h	/next186/
16	fixed OV/CY flags for IMUL	ndumitrache	3986d 05h	/next186/
15	doc fix	ndumitrache	3999d 20h	/next186/
14	generate invalid opcode exception for MOV FS and GS	ndumitrache	4027d 18h	/next186/
13	fix PUSHA SP pushed stack value, which should be the one before PUSHA	ndumitrache	4036d 05h	/next186/
12	fix IDIV when Q=0	ndumitrache	4070d 22h	/next186/
11	fix RET n alignment bug fix TRAP interrupt acknowledge updated specs	ndumitrache	4078d 05h	/next186/
10	fixed MUL/IMUL 8bit flags bug	ndumitrache	4114d 21h	/next186/
9	fixed DAA,DAS bug	ndumitrache	4133d 00h	/next186/
8	fixed DIV bug (exception on sign bit)	ndumitrache	4176d 23h	/next186/
7	fixed REP CMPS/SCAS bug when interrupted on the <equal> item	ndumitrache	4401d 06h	/next186/
6	updated CMPS/SCAS timing	ndumitrache	4401d 06h	/next186/
5	Fixed CMPS/SCAS bug when interrupted on the <equal> item	ndumitrache	4401d 06h	/next186/
4	comment fix	ndumitrache	4416d 07h	/next186/
3	updated comments	ndumitrache	4466d 05h	/next186/
2	v1.0	ndumitrache	4466d 22h	/next186/
1	The project and the structure was created	root	4467d 04h	/next186/