URL https://opencores.org/ocsvn/next186_soc_pc/next186_soc_pc/trunk

Subversion Repositories next186_soc_pc

[/] [next186_soc_pc/] - Rev 14

Rev	Log message	Author	Age	Path
14	Ported on Chameleon V2 board: Cyclone10LP-8, 32MB SDRAM at 185Mhz, 100Mhz bus, 50Mhz CPU, 90Mhz DSP, 8KB cache.	ndumitrache	1928d 18h	/next186_soc_pc/
13		ndumitrache	1928d 18h	/next186_soc_pc/
12		ndumitrache	2268d 19h	/next186_soc_pc/
11		ndumitrache	2319d 00h	/next186_soc_pc/
10	Adlib/OPL3 for Nexys4 board	ndumitrache	2604d 23h	/next186_soc_pc/
9		ndumitrache	2665d 17h	/next186_soc_pc/
8	Lattice Mach XO2 + SDRAM port (FleaFPGA)	ndumitrache	3670d 19h	/next186_soc_pc/
7	Disable interrupts in VESAMemControl callback	ndumitrache	3794d 18h	/next186_soc_pc/
6		ndumitrache	3974d 00h	/next186_soc_pc/
5	updated Next186 CPU	ndumitrache	3974d 00h	/next186_soc_pc/
4	fix BIOS int 1ah (Get system time)	ndumitrache	4005d 00h	/next186_soc_pc/
3		ndumitrache	4008d 02h	/next186_soc_pc/
2		ndumitrache	4008d 02h	/next186_soc_pc/
1	The project and the structure was created	root	4008d 19h	/next186_soc_pc/