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[/] [open8_urisc/] - Rev 175

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Rev Log message Author Age Path
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2975d 15h /open8_urisc/
174 Added ROM/RAM wrappers jshamlet 3170d 09h /open8_urisc/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3170d 09h /open8_urisc/
172 General code cleanup jshamlet 3170d 10h /open8_urisc/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3170d 10h /open8_urisc/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3170d 10h /open8_urisc/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3225d 10h /open8_urisc/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 4004d 07h /open8_urisc/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 4012d 05h /open8_urisc/
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4576d 06h /open8_urisc/
165 fixed issues with PC relative fixups in the linker khays 4577d 13h /open8_urisc/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4648d 01h /open8_urisc/
163 sync with binutils 2.22.51.20111114 khays 4685d 13h /open8_urisc/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4738d 18h /open8_urisc/
161 synchronize binutils/ with gnu dev tree of 2.21.53.20110828 khays 4762d 12h /open8_urisc/
160 synchronize binutils/gas with gnu dev tree of 2.21.53.20110828 khays 4762d 12h /open8_urisc/
159 synchronize binutils/gold with gnu dev tree of 2.21.53.20110828 khays 4762d 12h /open8_urisc/
158 synchronize binutils/opcodes with gnu dev tree of 2.21.53.20110828 khays 4762d 12h /open8_urisc/
157 synchronize binutils/ld with gnu dev tree of 2.21.53.20110828 khays 4762d 12h /open8_urisc/
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4795d 08h /open8_urisc/

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