OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 180

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
180 Added additional Open8 compatible modules jshamlet 1564d 18h /open8_urisc/
179 Replacing files accidentally deleted during check-in jshamlet 1574d 14h /open8_urisc/
178 Adding Open8 toolset for pure assembly jshamlet 1574d 14h /open8_urisc/
177 Fixed comments in RTC module jshamlet 2884d 18h /open8_urisc/
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2889d 16h /open8_urisc/
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2889d 21h /open8_urisc/
174 Added ROM/RAM wrappers jshamlet 3084d 15h /open8_urisc/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3084d 16h /open8_urisc/
172 General code cleanup jshamlet 3084d 16h /open8_urisc/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3084d 16h /open8_urisc/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3084d 16h /open8_urisc/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3139d 17h /open8_urisc/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3918d 13h /open8_urisc/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3926d 11h /open8_urisc/
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4490d 12h /open8_urisc/
165 fixed issues with PC relative fixups in the linker khays 4491d 19h /open8_urisc/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4562d 07h /open8_urisc/
163 sync with binutils 2.22.51.20111114 khays 4599d 19h /open8_urisc/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4653d 00h /open8_urisc/
161 synchronize binutils/ with gnu dev tree of 2.21.53.20110828 khays 4676d 18h /open8_urisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.