OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 182

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1567d 13h /open8_urisc/
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1568d 09h /open8_urisc/
180 Added additional Open8 compatible modules jshamlet 1572d 13h /open8_urisc/
179 Replacing files accidentally deleted during check-in jshamlet 1582d 09h /open8_urisc/
178 Adding Open8 toolset for pure assembly jshamlet 1582d 09h /open8_urisc/
177 Fixed comments in RTC module jshamlet 2892d 14h /open8_urisc/
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2897d 11h /open8_urisc/
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2897d 16h /open8_urisc/
174 Added ROM/RAM wrappers jshamlet 3092d 11h /open8_urisc/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3092d 11h /open8_urisc/
172 General code cleanup jshamlet 3092d 11h /open8_urisc/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3092d 11h /open8_urisc/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3092d 11h /open8_urisc/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3147d 12h /open8_urisc/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3926d 08h /open8_urisc/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3934d 06h /open8_urisc/
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4498d 07h /open8_urisc/
165 fixed issues with PC relative fixups in the linker khays 4499d 14h /open8_urisc/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4570d 02h /open8_urisc/
163 sync with binutils 2.22.51.20111114 khays 4607d 14h /open8_urisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.