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[/] [open8_urisc/] - Rev 184

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Rev Log message Author Age Path
184 More file/entity renaming to match private versions. jshamlet 1571d 02h /open8_urisc/
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1571d 02h /open8_urisc/
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1571d 02h /open8_urisc/
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1571d 23h /open8_urisc/
180 Added additional Open8 compatible modules jshamlet 1576d 02h /open8_urisc/
179 Replacing files accidentally deleted during check-in jshamlet 1585d 22h /open8_urisc/
178 Adding Open8 toolset for pure assembly jshamlet 1585d 22h /open8_urisc/
177 Fixed comments in RTC module jshamlet 2896d 03h /open8_urisc/
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2901d 00h /open8_urisc/
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2901d 05h /open8_urisc/
174 Added ROM/RAM wrappers jshamlet 3096d 00h /open8_urisc/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3096d 00h /open8_urisc/
172 General code cleanup jshamlet 3096d 00h /open8_urisc/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3096d 00h /open8_urisc/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3096d 00h /open8_urisc/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3151d 01h /open8_urisc/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3929d 21h /open8_urisc/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3937d 20h /open8_urisc/
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4501d 21h /open8_urisc/
165 fixed issues with PC relative fixups in the linker khays 4503d 04h /open8_urisc/

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