OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] - Rev 277

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
277 Fixed documentation errors related to flags. The UPP ALU instruction only alters the C flag, not the Z or N flags. This implies that using indexed loads or stores with auto post-increment will potentially alter the C flag. jshamlet 1426d 23h /open8_urisc/
276 More comment fixes jshamlet 1461d 20h /open8_urisc/
275 Fixed a minor comment error. jshamlet 1463d 14h /open8_urisc/
274 Updated comments with more corrections jshamlet 1463d 21h /open8_urisc/
273 Updated comments with corrections jshamlet 1463d 23h /open8_urisc/
272 Updated the HTML documentation to reflect the removed generic. jshamlet 1473d 22h /open8_urisc/
271 Removed deleted generic define. jshamlet 1473d 22h /open8_urisc/
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1473d 22h /open8_urisc/
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1476d 12h /open8_urisc/
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1476d 12h /open8_urisc/
267 Corrected the file description to indicate this is an example package. jshamlet 1476d 13h /open8_urisc/
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1476d 13h /open8_urisc/
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1568d 21h /open8_urisc/
264 Updated comments jshamlet 1578d 18h /open8_urisc/
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.		 jshamlet 1578d 19h /open8_urisc/
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1587d 22h /open8_urisc/
261 Increased delay timer to 7 bits for button press detection. jshamlet 1594d 22h /open8_urisc/
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1607d 21h /open8_urisc/
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.		 jshamlet 1607d 23h /open8_urisc/
258 Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. jshamlet 1608d 21h /open8_urisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.