OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] - Rev 167

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 4066d 04h /open8_urisc/trunk/
166 fixed additional issues with range checking on PCREL relocations for open8, added test cases to verify, catch tree up with binutils datestamp 20120301 khays 4630d 05h /open8_urisc/trunk/
165 fixed issues with PC relative fixups in the linker khays 4631d 12h /open8_urisc/trunk/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4702d 00h /open8_urisc/trunk/
163 sync with binutils 2.22.51.20111114 khays 4739d 12h /open8_urisc/trunk/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4792d 17h /open8_urisc/trunk/
161 synchronize binutils/ with gnu dev tree of 2.21.53.20110828 khays 4816d 11h /open8_urisc/trunk/
160 synchronize binutils/gas with gnu dev tree of 2.21.53.20110828 khays 4816d 11h /open8_urisc/trunk/
159 synchronize binutils/gold with gnu dev tree of 2.21.53.20110828 khays 4816d 11h /open8_urisc/trunk/
158 synchronize binutils/opcodes with gnu dev tree of 2.21.53.20110828 khays 4816d 11h /open8_urisc/trunk/
157 synchronize binutils/ld with gnu dev tree of 2.21.53.20110828 khays 4816d 11h /open8_urisc/trunk/
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4849d 07h /open8_urisc/trunk/
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.		 jshamlet 4850d 02h /open8_urisc/trunk/
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4855d 05h /open8_urisc/trunk/
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 4882d 01h /open8_urisc/trunk/
152 Correct the descriptions for GMSK and SMSK instructions in the Open8 Assembly Language Reference khays 4890d 03h /open8_urisc/trunk/
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4892d 04h /open8_urisc/trunk/
150 Updated the assembly language reference to add the CLR pseudo-mnemonic khays 4892d 11h /open8_urisc/trunk/
149 added clr "Clear Accumulator" pseudo-instruction khays 4892d 13h /open8_urisc/trunk/
148 catch up with binutils trunk through date-version 20110613 khays 4893d 07h /open8_urisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.