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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 167

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Rev Log message Author Age Path
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3924d 20h /open8_urisc/trunk/VHDL/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4560d 15h /open8_urisc/trunk/VHDL/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4651d 08h /open8_urisc/trunk/VHDL/
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4707d 23h /open8_urisc/trunk/VHDL/
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.		 jshamlet 4708d 18h /open8_urisc/trunk/VHDL/
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4713d 21h /open8_urisc/trunk/VHDL/
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 4740d 16h /open8_urisc/trunk/VHDL/
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4750d 19h /open8_urisc/trunk/VHDL/
10 corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values khays 4892d 04h /open8_urisc/trunk/VHDL/
8 Need to learn SVN... jshamlet 5220d 15h /open8_urisc/trunk/VHDL/
7 Initial Upload jshamlet 5220d 15h /open8_urisc/trunk/open8_urisc/VHDL/

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