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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 178

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Rev Log message Author Age Path
177 Fixed comments in RTC module jshamlet 2878d 03h /open8_urisc/trunk/VHDL/
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2883d 00h /open8_urisc/trunk/VHDL/
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2883d 05h /open8_urisc/trunk/VHDL/
174 Added ROM/RAM wrappers jshamlet 3078d 00h /open8_urisc/trunk/VHDL/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3078d 00h /open8_urisc/trunk/VHDL/
172 General code cleanup jshamlet 3078d 00h /open8_urisc/trunk/VHDL/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3078d 00h /open8_urisc/trunk/VHDL/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3078d 00h /open8_urisc/trunk/VHDL/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3133d 01h /open8_urisc/trunk/VHDL/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3911d 21h /open8_urisc/trunk/VHDL/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3919d 19h /open8_urisc/trunk/VHDL/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4555d 15h /open8_urisc/trunk/VHDL/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4646d 08h /open8_urisc/trunk/VHDL/
156 Optimized for timing,
Flattened block structure to single entity.		 jshamlet 4702d 23h /open8_urisc/trunk/VHDL/
155 Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path.		 jshamlet 4703d 17h /open8_urisc/trunk/VHDL/
154 Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. jshamlet 4708d 20h /open8_urisc/trunk/VHDL/
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 4735d 16h /open8_urisc/trunk/VHDL/
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4745d 19h /open8_urisc/trunk/VHDL/
10 corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values khays 4887d 04h /open8_urisc/trunk/VHDL/
8 Need to learn SVN... jshamlet 5215d 15h /open8_urisc/trunk/VHDL/

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