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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 186

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Rev Log message Author Age Path
186 Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. jshamlet 1560d 02h /open8_urisc/trunk/VHDL/
185 1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting		 jshamlet 1560d 05h /open8_urisc/trunk/VHDL/
184 More file/entity renaming to match private versions. jshamlet 1562d 04h /open8_urisc/trunk/VHDL/
183 Renamed core to o8_cpu to match new naming scheme jshamlet 1562d 05h /open8_urisc/trunk/VHDL/
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1562d 05h /open8_urisc/trunk/VHDL/
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1563d 01h /open8_urisc/trunk/VHDL/
180 Added additional Open8 compatible modules jshamlet 1567d 05h /open8_urisc/trunk/VHDL/
177 Fixed comments in RTC module jshamlet 2887d 06h /open8_urisc/trunk/VHDL/
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2892d 03h /open8_urisc/trunk/VHDL/
175 Added 4 and 8-bit LCD interfaces with backlight and contrast DACs jshamlet 2892d 08h /open8_urisc/trunk/VHDL/
174 Added ROM/RAM wrappers jshamlet 3087d 03h /open8_urisc/trunk/VHDL/
173 Added a couple of useful interfaces for detecting button presses and clock changes. jshamlet 3087d 03h /open8_urisc/trunk/VHDL/
172 General code cleanup jshamlet 3087d 03h /open8_urisc/trunk/VHDL/
171 Fixed comments for offsets 0x0 - 0x3 to indicate the read value jshamlet 3087d 03h /open8_urisc/trunk/VHDL/
170 Added 24-bit resolution epoch timer / alarm clock jshamlet 3087d 03h /open8_urisc/trunk/VHDL/
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3142d 04h /open8_urisc/trunk/VHDL/
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3921d 00h /open8_urisc/trunk/VHDL/
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3928d 22h /open8_urisc/trunk/VHDL/
164 Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. jshamlet 4564d 18h /open8_urisc/trunk/VHDL/
162 Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. jshamlet 4655d 11h /open8_urisc/trunk/VHDL/

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