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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 222

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222 Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. jshamlet 1514d 21h /open8_urisc/trunk/VHDL/
221 o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more. jshamlet 1515d 15h /open8_urisc/trunk/VHDL/
220 More revision sections added jshamlet 1515d 15h /open8_urisc/trunk/VHDL/
219 Added revision block and corrected creation date. jshamlet 1515d 16h /open8_urisc/trunk/VHDL/
218 Revision sections added,
vdsm8.vhd added.		 jshamlet 1515d 16h /open8_urisc/trunk/VHDL/
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.		 jshamlet 1515d 16h /open8_urisc/trunk/VHDL/
216 Fixed missing parenthesis jshamlet 1515d 18h /open8_urisc/trunk/VHDL/
215 More code cleanup jshamlet 1515d 18h /open8_urisc/trunk/VHDL/
214 Initial add of some older code jshamlet 1519d 16h /open8_urisc/trunk/VHDL/
213 Code and comment cleanup jshamlet 1519d 17h /open8_urisc/trunk/VHDL/
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1519d 23h /open8_urisc/trunk/VHDL/
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1520d 21h /open8_urisc/trunk/VHDL/
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1520d 23h /open8_urisc/trunk/VHDL/
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1521d 12h /open8_urisc/trunk/VHDL/
208 Removed unnecessary package references jshamlet 1521d 21h /open8_urisc/trunk/VHDL/
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1522d 14h /open8_urisc/trunk/VHDL/
206 Merged interrupt logic with other clocked process. jshamlet 1526d 09h /open8_urisc/trunk/VHDL/
205 More code and comment cleanup for the new SDLC engine jshamlet 1526d 09h /open8_urisc/trunk/VHDL/
204 Fixed more incorrect comments jshamlet 1526d 10h /open8_urisc/trunk/VHDL/
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1526d 16h /open8_urisc/trunk/VHDL/

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